The present invention relates in general to integrated circuits, and in particular to a high speed, low power amplifier circuit that is particularly suitable for use in semiconductor memories.
Higher density semiconductor memories are typically partitioned into a number of separate individual arrays. In Mega bit (e.g., 16M, 64M, or 256M) dynamic random access memories (DRAMs), for example, a typical individual array may include 256 rows (or word lines) and 1028 columns (or bit lines) of memory cells, to make a 256K individual array. Bit line sense amplifiers are located between arrays and may be shared by bit lines in two separate arrays. Each array also includes dedicated pairs of local data buses over which read and write transactions are carried out with selected bit line sense amplifiers. Bit lines are selected by decoding column addresses. The output of the column address decoder couples each pair of data buses to a single bit line sense amplifier. The number of pairs of local data buses in each array, the size and number of the arrays, the number of sense amplifiers all vary depending on the bit organization and type of memory architecture used.
A preferred technique to selecting bit line sense amplifiers in higher density memories has been to employ global column decoders. The outputs of a global column decoder typically extend over and are shared by multiple arrays. An output of the global column decoder, when asserted, couples the sense amplifier for the addressed column to a corresponding pair of local data buses in each array. However, data transaction occurs only in an array that is active. For the arrays that are not activated, all bit lines and local data buses are precharged to the same voltage level VBLP, which may be, for example, one half of the power supply voltage Vcc. Thus, in the inactive arrays, even if column decode switches are turned on to couple bit line sense amplifiers to local data buses, there should be no charge transferred since the bit lines and the data buses are all at the same precharge voltage level VBLP.
In the active array, an asserted global column decoder output turns on a column decode switch which is typically an n-channel transistor. Thus a selected bit line sense amplifier couples to a corresponding pair of data buses through the source/drain terminals of a pair of n-channel column switch transistors. In a read cycle, for example, the signal on the bit lines is transferred to the data buses, and is then sensed and amplified by a data bus sense amplifier. The output of the data bus sense amplifier is the read data that is transmitted to the output via a data output buffer.
Memory circuits commonly use the conventional differential amplifier with current-mirror loads, or dynamic differential amplifier with cross-coupled loads to implement the data bus sense amplifier. Such conventional data bus sense amplifiers commonly employ n-channel transistors as the differential input devices that receive the differential read data on the complementary data buses. It is well known that the voltage gain of such a differential amplifier with n-channel input devices is maximized when the common-mode voltage level is close to Vcc. Thus, for higher gain and faster operation, it is desirable to precharge the data bus input lines to the sense amplifier to a level closer to Vcc. Accordingly, many of today's multi-Mega bit memory circuits are designed such that the data buses in an activated array are charged up to close to Vcc, immediately before a read operation. During row address strobe (RAS) precharge cycle, the same data buses are discharged back down to VBLP. All data buses in inactive arrays remain at VBLP throughout the operation opening and closing a row.
Increased power consumption due to the repeated charging and discharging of the data buses, however, is one drawback associated with the Vcc-clamped data bus approach. In particular, as the memory density approaches Giga bit levels and the number of arrays that are active at the same time increases, this power consumption becomes a more serious concern.
Moreover, recently, memory circuits with a wide variety of design architectures and specifications have been developed, some of which require repeating this charge and discharge operation with the column cycle time period. Since the column cycle time period is one fifth or sixth of a typical RAS cycle time, power consumption increases yet further.
In general, with faster column cycle times (as in for example synchronous DRAM), and larger number of simultaneously active data buses (as in for example RAMBUS DRAM), the contribution of this charging and discharging of the data buses to power consumption becomes quite significant.
One might consider doing away with charging of the data buses to Vcc, and maintaining data bus precharge level at VBLP for a read operation. However, this approach poses other problems. Lowering the voltage level on the data buses from Vcc to about one half Vcc results in decreased drain-to-source voltage (Vds) across column decode switch transistors. This slows down the time it takes for the signal to develop on the data lines, adding to read cycle time.
A more serious problem with VBLP precharged data buses, however, is posed by the trend toward decreased power supply voltage levels. At 64 Mega bit levels, it is common to design the core of the memory circuit to operate at 2.5v, with a worst case value of 2.2v. Given a typical value of 0.8v for the threshold voltage of the NMOS transistor (Vtn), the turn-on voltage applied to the gate of NMOS input transistors of the data bus sense amplifier may be as low as (2.2v/2)-0.8v!=0.3v. The turn-on voltage can be actually somewhat lower because VBLP is typically smaller than Vcc/2 to improve the memory cell margin for storing a logic "1" level. At such reduced input voltages, the gain and the speed of operation of the data bus sense amplifier suffer significantly.
Employing low-Vtn devices at the input of the data bus sense amplifier appreciably increases the speed of operation. However, controlling the threshold level for low-Vt devices within the allowable limits has proven to be problematic in mass production. Moreover, such devices require additional masks and process steps, which makes the manufacturing process more complex and more expensive.
There is therefore a need for a fast and efficient sense amplifier circuit with lower power consumption.